Due to improvements in integrated circuit manufacturing capabilities, and to satisfy demand for increased integrated circuit usability and capability, such as the demand for increased functionality whilst preserving or improving on integrated circuit power requirements, integrated circuits are getting more and more complex over time. As with any product, these increased complexity ICs need testing to identify and eliminate errors and defects before and during mass production, or to just fully ascertain the functional capabilities of the integrated circuits prior to the product release, such as operating frequency.
Product testing for complex integrated circuits usually involves multiple test methods. For example, the scan-based automatic test pattern generation (ATPG) model for determining any ‘stuck-at’ fault(s) has been a standard test methodology for many years, but the fact that many ICs under test pass high coverage ‘stuck-at’ fault tests, but still fail to operate in normal conditions has led to the development of new, additional, test methodologies.
An example is the ‘at-speed (scan) test’ methodology, which is a form of integrated circuit testing that analyses integrated circuit operation to look for integrated circuit defects that result in speed or timing problems, such as crosstalk errors, path delay, and the like. These are particularly a problem at the more recent small manufacturing process nodes (e.g. 90 nm and smaller processes) now commonly used to manufacture integrated circuits, where the percentage of timing related defects is so high that static testing is no longer considered sufficient. At-speed scan testing, may be particularly associated with System on Chip (SoC) designs due to their increased complexity and therefore higher susceptibility to the causes of integrated circuit failure.
At-speed scan testing of integrated circuit designs typically has two portions. A first shift load-in data portion that is carried out at relatively low frequency, to load the test data patterns into the Integrated circuit under test, or portion thereof (e.g. scan chain). Then, a second portion comprising the integrated circuit being tested using this loaded in test data at a relatively high frequency (for example, at least at an intended operational frequency of the integrated circuit under test, but usually higher, in order to “push” the integrated circuit). The two portions may be carried out alternately with one another, with different test data patterns being loaded in in different shift load-in portions.
During at-speed scan testing of a particular integrated circuit under test, the current drawn by (or related power consumption of) the integrated circuit may be measured—and used to help determine if the integrated circuit has passed or failed the respective test.
Thus, at-speed scan testing of ICs involves, amongst other things, inputting test patterns to test for correct integrated circuit operation during normal use at high application frequencies, to thereby identify any erroneous operation, including excessive power use, due to issues such as outright mis-design of the integrated circuit, wire delay, crosstalk, and the like. These at-speed scan tests can also help determine a maximum safe operating frequency for a particular integrated circuit. Thus, at-speed scan testing not only occurs at the intended operating frequency of an integrated circuit, but also helps to determine what that intended operating frequency should be.